The invention pertains to a method for the exchange of signals between modules connected via a common bus and to a device for implementation of the method. Conventional computers have several hardware modules which are connected to a common bus, such as the known ISA bus or PCI bus. In order to exchange particular signals between the individual bus users, additional lines are provided for special purposes, such as special interrupt lines, via which individual modules can request an interrupt from the CPU. The number of such lines increases as a function of the number of modules that can request an interrupt. The more complex the system, the more lines are needed, which causes the wiring expense to rise enormously. In addition to the mentioned interrupt lines, in more complicated systems, even more lines are provided for special purposes and for direct exchange of information between individual modules. These lines are hard wired and cannot later be changed or expanded. Thus, the amount of the information that can be passed between individual modules is limited in these known systems.
The purpose of the present invention is to improve the method and the device of the type discussed above in a thorough manner so that any amount of information can be exchanged between individual modules without additional expense for lines.
This problem is solved by the method with the properties stated in claim 1 and by the device with the properties stated in claim 7. Advantageous configurations and refinements of the invention are presented in the subordinate claims.
The basic principle of the invention concerns the exchange of information via a common bus. For the exchange of information between modules, no dedicated lines are needed for certain signals, such as for interrupts, DMA (direct memory accesses), etc. Bus users (modules) of this kind required to send information request access to the bus (bus request on a single common line), whereupon a clock-controlled cycle is started. This cycle is executed, for example, as an instruction (RAK instruction) and consists of an RAK command that initiates the cycle and of one or more RAK cycles, each having the length of one clock cycle. A predefined period of time of preferably the length of one clock cycle is assigned to each module within which it will send its information over at least one bus line. During this predefined time period, several modules can be addressed simultaneously if different bus lines are assigned to them. It is also possible to allocate several bus lines to one module within one RAK instruction. The individual bus users can also be addressed in temporal succession. The given bus user that has sent the request signal thus sends its information within the time window of the cycle assigned to it via a previously defined line. Each bus user is thus so configured that it can send or receive signals within one or more predetermined time windows. Several bus users can be addressed to act as receivers even within one and the same clock cycle and respective time window. Conversely, a bus user which wants to send different messages to various other bus users can send these messages within one full cycle at different time windows to which the receiver modules are configured.
In general we should mention that the concept of xe2x80x9cmodulexe2x80x9d generally pertains to individual bus users, which can be designed as both a plug-in assembly or an IC (chip). Thus, the invention can also be used for the exchange of information between individual chips which are integrated in one assembly, and then these chips can communicate with each other via the bus.
If one bus user has sent a request signal, then the current bus master (e.g., the CPU or another module which is the current bus master) will terminate or interrupt its current bus activity and release the bus for a short time, so that the bus user which has made the bus request can transmit its signals. Then the bus master or another module can again use the bus.
During one such cycle, any number of bus users can send signals within their time window or windows, and during the remaining time segments of the cycle, they can receive signals from other bus users. With the invention, the following advantages, among others, can be realized:
No additional bus lines are needed besides the request line, and if necessary, one additional control line (RAK).
Any number of signals can be transmitted.
All types of signals can be transmitted and not only interrupt requests or DMA transmissions (direct memory access)
All bus users can transmit signals to all others.
One bus user can send a signal, for instance, and all others can receive it. For example, higher-order system signals, such as pending voltage loss or occurring bus error, can be signaled to all bus users.
The connections between the bus users can be configured by software and can be reconfigured at any time. Any expansions, such as in the number of signals, merely require a new software configuration.
In bus systems that are DMA or bus master capable, the same method can be used. The slight additional load on the bus due to this transmission or due to these transmissions is no longer a considerable matter.
All bus users are thus each individually connected to each other via the bus. There are no function-related or user-specific lines or any other supplemental lines (with the exception of a request line and perhaps the RAK line).
Each bus user consists of a functional unit and a bus interface, hereinafter called the BIU (for bus-interface unit). The BIU is a circuit used to connect the bus user to the bus. It performs certain activities involving the bus, but without having to involve the functioning unit. For example, if a bus user A or its functional unit determines that the state of a particular signal has changed, then it will report this to its BIU. The BIU has been previously configured so that this change will be reported to one or more bus users (clock timing and line). The BIU of the bus user A will now set the bus-request signal as active (enabled). The bus user B which is currently using the bus or which is allowed to use it is the current bus master. It recognizes the bus request, ends or interrupts its current bus activity, and carries out the following bus activities, wherein the functional unit of the bus master xe2x80x9cnoticesxe2x80x9d nothing, except that it cannot use the bus for the moment. The BIU of the current bus master B sends an RAK command (so-called RAK stands for request acknowledge) to the bus or signals it via an additional bus line. All connected BIUs recognize this command, as does the BIU of the bus user A. Next, in accordance with the configuration, one or more so-called RAK cycles (for request acknowledge) will be carried out. If the RAK cycle is at the point for which the bus user A was configured, then its BIU applies the state of the signal to the bus line for which the BIU of A was configured. The bus line is at this time viewed as a virtual interconnection line (VIL) between modules. All other lines leave it unaffected (tri-state). During each RAK-cycle, a number of signals can be transmitted according to the size of the bus. The number of RAK cycles in an RAK instruction is then the number of the defined lines (VIL) divided by the bus size. The bus user A also notices that the change in the signal was transmitted and then ends the process. All other bus users, if appropriately configured, observe these RAK cycles and thus determine whether a signal is being sent to it. If this is the case, then they store the passed information. This concludes the process.
In principle, there are two types of signals to be passed:
1. State of a signal
After every change in the state of the signal, a bus request will be triggered with subsequent RAK instruction. In this case, the current state of the signal will be reported via the bus lines.
2. Change of a signal from logical xe2x80x9c0xe2x80x9d to logical xe2x80x9c1xe2x80x9d (rising edge)
If a signal has a rising edge, then a bus request will be triggered with the following RAK instruction. In this case, it will be reported via the bus lines whether the edge has arrived (=1) or not (=0)
For each bus request with following RAK instruction, all signals will always be transmitted. But it is also possible to adjust the number of RAK cycles dynamically, that is, to terminate after the desired signal was transmitted. If a bus request with following RAK cycle is triggered by a third bus user, then in the case of the other signals which are configured for xe2x80x9cstate,xe2x80x9d the current state will also be transmitted. With regard to the signals which are configured for xe2x80x9cedge,xe2x80x9d a logical xe2x80x9c0xe2x80x9d will be passed, i.e., no edge has appeared. Also, several signals from different bus users can initiate a bus request. Then they will be served in a single RAK instruction.
For the RAK cycles it is clear that one and the same RAK cycle within an RAK instruction can be used by several bus users according to the configuration and the bus size. In the RAK cycle of one bus user, one or more lines can be provided, where, in the extreme case, the corresponding bus user uses all bus lines in its RAK cycle, and in this case, only this one bus user will have access to the RAK cycle. In the other extreme case, in which only one line is assigned in an RAK cycle for these configured bus users, as many bus users can transmit in this cycle as there are bus lines available.
With the invention it is also possible to operate a multi-master-capable bus. The determination of the particular master is performed according to the same principle. A bus user that wants to become the new bus master must first fetch the bus. In this case, it will likewise enable the bus-request-line, and the BIU of the still current master will execute an RAK instruction. The new bus master will send a corresponding signal during the cycle assigned to it, via the line assigned to it. If several bus users intend to become new bus masters, then they all place this request on the corresponding bus lines during their assigned cycle. The BIU of the current bus master then determines which ones will obtain the bus. The algorithm for this is programmed and is specified by the configuration master in the initialization phase.